现代开源`ASIC/FPGA`工程链路使用经验分享

December 28, 2024

现代开源ASIC/FPGA工程链路使用与经验分享 #

工欲善其事，必先利其器 #

金宇 ysyx_23060087

About this sharing #

• 主要介绍现代开源ASIC/FPGA工程链路的个人使用经验，高度概括和综述
• 免责声明：本人主要的ASIC/FPGA工程链路使用经验来自于ysyx项目的开发实践
  • 本人主业上无IC设计背景，其中使用的工具或者看法可能不是最优的
  • 每个人的工程链路使用习惯可能不同，欢迎交流
• “一生一芯” 2023年10月至今｜通过C认证，学号：ysyx_23060087，https://docs.qq.com/sheet/DRkdzQ0xsVFNvdEhF
• 软件：完成RV32/64IM行为模拟器NEMU，能够运行RT-Thread，nanos-lite (PA4.2)
• 硬件：完成多周期顺序4集单发射流水线 RV32IM 处理器设计和开发，个人额外还实现了FPGA移植（Tang-nano-20k），基于OpenSTA的PPA评估。 (SystemVerilog)

Documentation: riscv-unified-db #

https://riscv-software-src.github.io/riscv-unified-db/manual/html/landing/index.html

Documentation: rvcodecjs #

https://luplab.gitlab.io/rvcodecjs/

Software Engineering #

• Conventional Commits: feat: finish pa4.1, fix: axi4 write stall

<type>[optional scope]: <description>
...

• Semantic Versioning 2.0.0 | Semantic Versioning

版本格式：主版本号.次版本号.修订号，版本号递增规则如下：
1. 主版本号：当你做了不兼容的 API 修改，
2. 次版本号：当你做了向下兼容的功能性新增，
3. 修订号：当你做了向下兼容的问题修正

Software Engineering #

• Keep a Changelog

Compile: RTL -> Syn -> PnR (FPGA) #

• RTL sim: verilator, https://github.com/verilator/verilator
  • fst wave format, microbenchmark: npc 23 MB，ysyxsoc 71 MB (vcd N GB)
    • https://veripool.org/guide/latest/faq.html#how-do-i-generate-fst-waveforms-traces-in-c-or-systemc
• Syn: YosysHQ/yosys: https://github.com/YosysHQ/yosys

yosys ltp -noff
yosys show -format dot -prefix ./out/${mod_name} -viewer none

• PnR: YosysHQ/nextpnr https://github.com/YosysHQ/nextpnr (Gowin 高云 FPGA)
  • https://github.com/Kingfish404/ysyx-workbench/tree/master/fpga/gowin-tang-nano-20k

Verification & Tools #

• formal:
  • symbiyosys
    • ysyx docs: i cache verification
    • my case: AXI4 verification, multi-cycle mul/div verification (equ. check)
• Tools:
  • waveviewer: surfer, https://gitlab.com/surfer-project/surfer
  • fpga loader: openFPGALoader, https://github.com/trabucayre/openFPGALoader
  • sd cards flashing: balenaEtcher, https://github.com/balena-io/etcher

Tools: surfer - Waveform Viewer #

IDE #

• IDE: vscode, https://github.com/microsoft/vscode

VSCode Extension - 0 #

• vscode extension:
  • Verilog-HDL/SystemVerilog/Bluespec SystemVerilog
    • https://marketplace.visualstudio.com/items?itemName=mshr-h.VerilogHDL
    • https://github.com/mshr-h/vscode-verilog-hdl-support
  • Verible
    • https://marketplace.visualstudio.com/items?itemName=CHIPSAlliance.verible
    • https://github.com/chipsalliance/verible

VSCode Extension - 1 #

• Scala (Metals)
  • https://marketplace.visualstudio.com/items?itemName=scalameta.metals
  • https://github.com/scalameta/metals-vscode
• Scala Syntax (official)
  • https://marketplace.visualstudio.com/items?itemName=scala-lang.scala
  • https://github.com/scala/vscode-scala-syntax
• vscode extension (closed source):
  • Serial Monitor
    • https://marketplace.visualstudio.com/items?itemName=ms-vscode.vscode-serial-monitor

Install the tools - via homebrew or oss-cad-suite-build #

Homebrew or YosysHQ/oss-cad-suite-build