(u)arch Side Channel Attacks
Research主要统计安全四大（S&P，CCS，USENIX Security，NDSS）做侧信道攻击且在CPU的论文，检测/防御不列出.
Tier 1 Conference
- S&P (Oakland) IEEE Symposium on Security and Privacy
- CCS ACM Conference on Computer and Communications Security
- Security USENIX Security Symposium
- NDSS ISOC Network and Distributed System Security Symposium
(Frontend): Frontend related (Cache): Cache related, includes TLB, Page, etc (Timing): Timing related (Other): Other
2023
- (Cache)SecSMT: Securing SMT Processors against Contention-Based Covert Channels | USENIX
- (Cache, Timing)Side-Channel Attacks on Optane Persistent Memory | USENIX
2022
- (Cache, Timing)A Systematic Look at Ciphertext Side Channels on AMD SEV-SNP | IEEE Conference Publication | IEEE Xplore
- (Cache, Timing)Adversarial Prefetch: New Cross-Core Cache Side Channel Attacks | IEEE Conference Publication | IEEE Xplore
- (Cache, Timing)MeshUp: Stateless Cache Side-channel Attack on CPU Mesh | IEEE Conference Publication | IEEE Xplore
- (Other)Frequency Throttling Side-Channel Attack
- (Cache, Timing)Microarchitectural Leakage Templates and Their Application to Cache-Based Side Channels
- (Other)On the Success Rate of Side-Channel Attacks on Masked Implementations
- (Cache, Timing)Targeted Deanonymization via the Cache Side Channel: Attacks and Defenses | USENIX
- (Cache, Timing)Binoculars: Contention-Based Side-Channel Attacks Exploiting the Page Walker | USENIX
- (Other)Don't Mesh Around: Side-Channel Attacks and Mitigations on Mesh Interconnects | USENIX
2021
- (Other)Invisible Probe: Timing Attacks with PCIe Congestion Side-channel | IEEE Conference Publication | IEEE Xplore
- (Other)PLATYPUS: Software-based Power Side-Channel Attacks on x86 | IEEE Conference Publication | IEEE Xplore
- (Other)Automatic Extraction of Secrets from the Transistor Jungle using Laser-Assisted Side-Channel Attacks | USENIX
- (Other)Lord of the Ring(s): Side Channel Attacks on the CPU On-Chip Ring Interconnect Are Practical | USENIX
- (Cache, Timing)Prime+Probe 1, JavaScript 0: Overcoming Browser-based Side-Channel Defenses | USENIX
- (Other)CIPHERLEAKS: Breaking Constant-time Cryptography on AMD SEV via the Ciphertext Side Channel | USENIX
- (Frontend, Timing)Frontal Attack: Leaking Control-Flow in SGX via the CPU Frontend | USENIX
2020
- (Cache, Timing)HybCache: Hybrid Side-Channel-Resilient Caches for Trusted Execution Environments | USENIX
- (Other)ABSynthe: Automatic Blackbox Side-channel Synthesis on Commodity Microarchitectures - NDSS Symposium
2018
- (Other)FPGA-Based Remote Power Side-Channel Attacks | IEEE Conference Publication | IEEE Xplore
- (Other, Timing)Ohm’, s Law in Data Centers: A Voltage Side Channel for Timing Power Attacks
- (Frontend, Timing)Nemesis: Studying Microarchitectural Timing Leaks in Rudimentary CPU Interrupt Logic
- (Cache, Timing)Translation Leak-aside Buffer: Defeating Cache Side-channel Protections with TLB Attacks | USENIX